PhD and MSc Theses

PhD and MSc Theses, since 1988

Advisor Professor Ran Ginosar
Advisor's Email ran@ee.technion.ac.il
Advisor's Home-Site http://www.ee.technion.ac.il/people/ran/
No of theses 64
Department Electrical Engineering
Department Web Site webee.technion.ac.il/hebrew
Student's Name Graduation Year Degree Abstracts Research Name
Morad Amir 2016 PhD Abstracts Multicore and Processing-in-Memory Architectures
Rotem Efraim 2015 PhD Abstracts High Performance Computing in Physically Constrained Environment
Beer Gingold Salomon Michel 2014 PhD Abstracts Metastability and Synchronization in VLSI systems
Yavits Leonid 2015 PhD Abstracts Analysis and Optimization of Parallel Computing Architectures and in-Memory Computing
Dobkin Rostislav 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC
Morgenshtein Arkadiy 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect
Bolotin Evgeny 2007 PhD Abstracts Network on Chip
Perelman Yevgeny 2007 PhD Abstracts The Neuroprocessor: An Integrated Interface to Biological Neural Networks
Kol Rakefet 1998 PhD Self-Timed Asynchronous Architecture of an Advanced General Purpose Microprocessor
Harsat Arie 1993 PhD Llsi Architectures for Flat Concurrent Prolog
Nathan Abraham 1989 MSc Compilation of Fcp to Carmel and Its Performance Analysis
Yankilevich Yevgeny 2018 MSc Abstracts Fast and Efficient Soft Errors Detection and Correction in CAM and TCAM
Ramadan Misbah 2017 MSc Abstracts Adaptive Programming for Multi-Level Cell ReRAM
Kaplan Roman 2016 MSc Abstracts Accelerating SpMV Multiplication using Compression on the Plural Many-Core Architecture
Nassar Mohammad 2015 MSc Abstracts Many-Core Architecture
Diamant Ron 2015 MSc Abstracts Asynchronous Sub-threshold Ultra-low Power Processor
Zhang Yongxin 2015 MSc Abstracts High Speed Receiver Circuit for On-Chip Communications
Manor Shimon 2013 MSc Abstracts Multi-Synchronous Clocking for Low Power
Adato Avi 2013 MSc Abstracts Design Methods to Reduce Radiation Effects on Electronic Circuits
Nahmanny Danniel 2013 MSc Abstracts High-Speed, Currnet-Mode, Serial Link Communication
Verbitsky Dmitry 2013 MSc Abstracts Automatic Recognition and Verification of Handshake-Based Synchronizers
Jacob Prarthana 2013 MSc Abstracts Testing of a Fast on Chip Serial Link
Naveh Alon 2013 MSc Abstracts Power Aware Scheduling in a Heterogeneous Processor
Cohen Yaron 2012 MSc Abstracts Low Power D/A Converter Design Considerations
Avron Itai 2012 MSc Abstracts Scheduler Performance in Many-core Architecture
Nave Eyal-Itzhak 2012 MSc Abstracts TCP Window Based Dynamic Voltage and Frequency Scaling (DVFS) for Low Power Communication Network Controller System on Chip (SoC)
Abdelhadi Ameer 2011 MSc Abstracts Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks
Friedman Eyal 2011 MSc Abstracts Processor-to-Memory Non-Equidistant Network in a Many-Core Architecture
Khoretz Dmitri 2011 MSc Abstracts Cores and Memory Performance of HyperCorex: Many-Core Architecture
Vainbrand Dmitri 2010 MSc Abstracts Network-on-Chip Architecture for Neural Networks
Vaisband Inna 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction
Baron Asaf 2008 MSc Abstracts The Capacity Allocation Paradox
Kayam Michael 2007 MSc Abstracts Synchronizers for Low Voltage and Low temerature Operation
Tolchinsky Michael 2007 MSc Abstracts Implementation of New Method of Measurement for Metastability Coefficient for Flip-flops
Elyada Avshalom 2007 MSc Abstracts Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Yekutieli Ziv 2007 MSc Abstracts Integrated Multi-Electrode Array: An Interface to Ex Vivo Neural Networks
Lyakhov Alexander 2006 MSc VLSI Sensor Chip for In-Vitro Measurement of Biological Neural Network Activity
Kapschitz Yitschak 2006 MSc Abstracts Formal verification of synchronizers
Walter Isask'har 2006 MSc Abstracts Quality of Service in Network on-Chip
Frank Uri 2005 MSc Abstracts A Predictive Synchronizer for Bridging Different Frequency Clock Domains
Obridko Ilya 2005 MSc Abstracts Minimal Energy Asynchronous Adder Architectures
Zviagintsev Alex 2005 MSc Abstracts Hardware Algorithms and Architectures for Power Spike Detection and Sorting
Tamir Guy 2004 MSc Abstracts Synchronizers Metastability
Semiat Yaron 2003 MSc Abstracts Design, Implementation and Test of Adaptive Synchronization Circuits
Katz Sagi 2003 MSc Abstracts Polyhedral Surface Decomposition and Applications
Dobkin Rostislav 2003 MSc Abstracts Parallel VLSI Architecture and Parallel Interleaver Design for MAP Turbo Decoder
Elboim Yaron 2002 MSc A Clock Tuning Circuit for System-on-Chip
Perelman Yevgeny 2001 MSc A Low-Light Sensor for Medical Diagnostic Applications
Shpolyansky Boris 1999 MSc Improving of Performance of Superscalar Microprocessors Using Scheduling History
Finkelstein Hod 1998 MSc Frontside-Bombarded Metal-Plated Electron Radiation Imaging Chip Fabricated in Cmos Technology
Sherman Marina 1997 MSc Intelligent-Scan Based Transmission and Retrieval of Images
Freizeit Amir 1995 MSc Hierarchical Conditional Replenishment Video Compression Algorithm and Architecture
Chen-Levy Sarit 1995 MSc Adaptive Sensitivity Ccd Image Sensor
Yavits Leonid 1995 MSc Architecture and Design of An Associative Processor Chip
Weinberg Nitzan 1995 MSc A Neural Network Architecture for Image Processing
Wolf Stuart 1992 MSc Development of a Colour Enhancealgorithm Using Spatial Proce
Gur Shimon 1990 MSc Design of Carmel 2 and Its Implementation with Silicon
Yadid-Pecht Orly 1990 MSc An Lmaging System with Random Access
Rotman Alan 1989 MSc Control Unit Syntesis from a High Level Language
Friedlander Baruch-Ram 1989 MSc Vlsi Architecture for Morphological Operations
Kol Rakefet 1989 MSc Self-Timed Finite-State Machines
Alon Dov 1989 MSc Switch Controller for Mp/l Parallel Processor
Mintz Aviad 1989 MSc Design of Vlsi Prolessor for Hough Transform
Telichevesky Ricardo 1988 MSc A Vlsi Architecture for Fntelligent Scan Image Processing